仕事内容
- Perform statistical analysis on test data, correlation analysis for failure isolation from various perspectives (e.g., design, test, process), then take an appropriate corrective action by working with design team, test team and foundry, respectively. - Work with foundry to keep stable yield by statistical product control, and manage DOE (Design of Experiment) for further yield improvement from wafer process perspective. - Work with foundry to run failure analysis which includes the failure mode caught at wafer level test, qualification, characterization, downstream test and field return. - Manage the characterization activities; make a plan with design team, prepare characterization test program with test team, make the instruction for foundry, analyze data over PVT. - Manage the qualification activities (e.g., ESD, Latch-up, HTOL); make a plan with design team, prepare Pre/Post test program with test team, make the instruction for foundry, analyze data before and after stress. - Optimize the test limit by considering the guard-band specifications based on characterization, qualification and GR&R data. - Additional tasks might be required, depending on business situation.
リクエスト
The ideal candidate should have 10+ years of product engineering experience.Knowledge of silicon wafer process, test, characterization and qualification.Experiences in yield and quality management through the development and mass production of new IC.Knowledgeable in statistical product control (e.g., lot disposition).Ability to manage DOE (Design of Experiment) for problem solving (e.g., yield improvement based on the failure analysis).Knowledge of the basics of semiconductor devices and chip design, experience to work with design team.Business level English communication skills to work with internal team and foundry.
住所
Japan
